Chang-Chi Lee, Hou-Ming Chen, Chi-Chang Lu, Bo-Yi Lee, Hsien-Chi Huang, He-Sheng Fu and Yong-Xin Lin, “A High-Precision Bandgap Reference with a V-Curve Correction Circuit,’’ IEEE Access, vol. 8, pp. 62632-62638, April 2020. (SCI)
Chi-Chang Lu and Ding-Ke Huang, “A 10-bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme,’’ IEEE Access, vol. 8, pp. 28257-28266, Feb. 2020. (SCI)
Chi-Chang Lu and Ding-Ke Huang, “A 1.2-V 10-bits 40-MS/s CMOS SAR ADC for Low-Power Applications,” IET Circuits, Devices & Systems, vol. 13, no. 6, pp. 857-862, Sept. 2019. (SCI)
Chi-Chang Lu and Hou-Ming Chen, “SC Amplifier and SC Integrator with Enhanced Immunity to Capacitor Mismatch,” Analog Integrated Circuits and Signal Processing, vol. 96, no. 3, pp. 509-519, Sept. 2018. (SCI)
Chi-Chang Lu, “A 1.2 V 10-bit 5MS/s Low Power CMOS Cyclic ADC Based on Double-Sampling Technique,” Analog Integrated Circuits and Signal Processing, vol. 81, no. 1, pp. 137-143, Oct. 2014. (SCI)
Tsung-Sum Lee and Chi-Chang Lu, “A 0.6-V Subthreshold-Leakage Suppressed Fully Differential CMOS Switched-Capacitor Amplifier,” Analog Integrated Circuits and Signal Processing, vol. 74, no. 2, pp. 409-416, Feb. 2013. (SCI)
Chi-Chang Lu, “A 1.5V 10-b 30-MSamples/s CMOS Pipelined Analog-to-Digital Converter,” Analog Integrated Circuits and Signal Processing, vol. 68, no. 3, pp. 341-347, Sept. 2011. (SCI)
Tsung-Sum Lee and Chi-Chang Lu, 2011, “A 330 MHz 11 bit 26.4 mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold Circuit,” Circuits, Systems and Signal Processing, vol. 29, no. 2, pp. 883-898, Apr. 2011. (SCI)
Tsung-Sum Lee and Chi-Chang Lu, “Two 1-V Fully Differential CMOS Switched-Capacitor Amplifiers,” Circuits, Systems and Signal Processing, vol. 29, no. 2, pp. 195-207, Apr. 2010. (SCI)
Tsung-Sum Lee and Chi-Chang Lu, “A 250MHz 11bit 22mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold Circuit,” Analog Integrated Circuits and Signal Processing, vol. 58, no. 2, pp. 105-113, Feb. 2009. (SCI)
Chi-Chang Lu and Tsung-Sum Lee, “A 10-bit 60-MS/s Low-Power CMOS Pipelined Analog-to-Digital Converter,” IEEE Transactions on Circuits and Systems II, vol. 54, no. 8, pp. 658-662, Aug. 2007. (SCI)